The new processor is built around processing network workloads to take the load off the CPU. Credit: geralt Intel has launched a field-programmable gate array—Agilex 7 with R-Tile—that features PCIe 5.0 and CXL capabilities for processing networking workloads. The Agilex FPGA is primarily used in smartNICs that offload the processing of network traffic from the CPU, thus freeing up CPU capacity for other tasks. Intel sees Agilex playing a role in data centers, telecommunications, and financial services, among other high-traffic industries. Agilex is an evolution of the old Stratix and Arria FPGA lines, and it’s designed to reflect changes in performance and features. Agilex 7 is the second most powerful FPGA family within the Agilex portfolio. With this release, Agilex has undergone quite a change. The previous version was a PCI Express 4.0 product, built on a Stratix 10 DX design at 14nm. This new version supports PCI Express 5.0, and uses a chiplet design that breaks down the silicon into multiple smaller chips on the 7nm process. With Intel’s chiplet approach, Agilex 7 with R-Tile combined with the F-Tile, which was announced earlier this year, offers 116Gbps of transceiver bandwidth, the fastest throughput yet among Intel FPGAs. It also supports hard IP, which means functions like memory controllers and digital signal processors are hard coded into the silicon, rather than soft IP, which is programmed. The IP can’t be modified, but it also performs much faster and reduces design time for developing and deploying products. The R-Tile is part of the new chiplet design where the chiplets are connected by a high-speed interconnect. R-Tile is a companion chip to the FPGA that specifically supports high-speed PCI Express connections and integrates with CPUs to accelerate high-performance computing workloads. Agilex 7 supports CXL 1.1 and will support next generation CXL 2.0-capable CPUs when they ship. CXL is a high-speed interconnect that allows direct memory-to-memory communication for data sharing without having to go through CPUs and buses. Intel is saying that Agilex 7 builds now support CXL 1.1, and will support selected CLX 2.0 features pending validation, interoperability, and qualification with future CPUs. Agilex 7 is shipping to OEM customers now. Related content news High-bandwidth memory nearly sold out until 2026 While it might be tempting to blame Nvidia for the shortage of HBM, it’s not alone in driving high-performance computing and demand for the memory HPC requires. By Andy Patrizio May 13, 2024 3 mins CPUs and Processors High-Performance Computing Data Center news CHIPS Act to fund $285 million for semiconductor digital twins Plans call for building an institute to develop digital twins for semiconductor manufacturing and share resources among chip developers. By Andy Patrizio May 10, 2024 3 mins CPUs and Processors Data Center news HPE launches storage system for HPC and AI clusters The HPE Cray Storage Systems C500 is tuned to avoid I/O bottlenecks and offers a lower entry price than Cray systems designed for top supercomputers. By Andy Patrizio May 07, 2024 3 mins Supercomputers Enterprise Storage Data Center news Lenovo ships all-AMD AI systems New systems are designed to support generative AI and on-prem Azure. By Andy Patrizio Apr 30, 2024 3 mins CPUs and Processors Data Center PODCASTS VIDEOS RESOURCES EVENTS NEWSLETTERS Newsletter Promo Module Test Description for newsletter promo module. Please enter a valid email address Subscribe